Modern FPGA fabric architecture consists of programmable segmented routing and programmable logic blocks. Segmented routing usually consists of routing wires in different lengths in vertical and horizontal directions. For example, the x1 length can reach the next tile and the x2 length can reach 2 tiles away. Shorter routing usually provides more routing flexibility and lower metal channel usage, but shorter routing can cause performance to be slower. The use of longer routing is faster for longer distance connections, but more costly in terms of die size and less flexibility in terms of connectivity. Overall, FPGA programmable routing is costly in die size, slow in performance, and more power hungry than other ASIC and ASSP solutions in the same process technology.
FIG. 1 represents a typical FPGA architecture model upon which most modern FPGAs are based. Referring to FIG. 1, the connection block (“C” Block) provides input and output multiplexing (muxing) connections from the corresponding logic block to vertical and horizontal routings. The switch block (“S” Block) provides the vertical and horizontal routing connections to stitch routing segments together. Routing resources have various segmentation lengths to provide different tradeoffs between routing density, connection flexibility, performance, etc.
Generally, since an FPGA has the same routing density across the entire array, routing count per row or column is set by the worst-case routing congestion. This is quite wasteful given that most locations would require routing density much lower than the worst-case locations.
Another challenge with modern FPGAs is that the advanced process technology node has very resistive metal interconnects even though the transistors contained therein are getting faster. This affects the overall FPGA performance significantly, given that routing delay limits FPGA performance and resistive metal interconnect slows down longer routing significantly. In order to compensate of this effect, modern FPGAs use wider metal wires to lower resistance for performance, which in turn consumes even more area and power.